Year 3 Report on TDC Performance and ASIC Tile Controller Design

Abstract

The tile controller (TC) is a device that supports the readout of arrays of three-dimensional photon-to-digital converters (3D PDCs), and its presence is necessary whenever arrays of 3D PDCs are used. Its main function is to provide communication between 3D PDC chips and a data acquisition system. In particular, the TC will capture SPAD tagging and time of arrival information and program SPAD masking and operating parameters. Of the many functions required of the TC, doubtless the most important is accurately identifying the arrival times of photons with a precision that is either comparable or superior to that of the SPADs themselves. Because of this importance, the development of the TC followed a path that dedicated particular attention to the development of the main timing element: the time-to-digital converter (TDC). This device identifies the time of arrival of an event with great precision (in our case, ~10’s of ps) and converts the time of arrival into an analog amplitude that can be converted into a digital number that represents the time. Different designs for the TDC were evaluated to identify the best power/performance compromise for the application. The designs were implemented in silicon and thoroughly evaluated and documented. Each step along the way was prototyped using a field-programmable gate array (FPGA) development kit. The use of this kit enabled on-the-fly changes and their verification with little marginal effort since the code utilized to implement the digital functions in the FPGA kit can almost directly generate the hardware functions in the TDC silicon chip. Heavy reliance on this kit ensured short design cycles for silicon chips with minimal or no costly errors in the implementation. In this report, each step in the design cycle will be described and discussed.