- By:
- Ribeiro, Pedro Eugenio M; Xue, Lingxiao ; Ozpineci, Burak ; Chowdhury, Md S; Galigekere, Veda Prakash ; Su, Gui-Jia ; Barua, Himel
- Page Number:
- 7192-7196
- Book Title:
- 2024 IEEE Energy Conversion Congress and Exposition (ECCE)
- Publication Date:
- March 12, 2026
- Publisher Location:
- IEEE, New Jersey, United States of America
- Conference Name:
- 2024 IEEE Energy Conversion Conference and Exposition (ECCE 2024)
- Conference Location:
- Phoenix, Arizona, United States of America
- Conference Sponsor:
- IEEE
- View DOI Listing:
- https://doi.org/10.1109/ECCE55643.2024.10861292
Abstract
Minimizing parasitic inductance of power modules is needed to advance their electrical performance. Innovation in the past decade has driven down the inductance of SiC half-bridge power modules to around 1–2 nH by using multilayer, embedded, and hybrid structures. Further reduction becomes difficult, mainly limited by the excessive interconnects required for the planar placement of vertical conducting chips. To address this, a vertically stacked-die approach is proposed in this paper, taking advantage of the vertical conducting nature of the SiC chips. With ceramic decoupling capacitors integrated, 0.48 nH overall loop inductance is achieved and validated by experimental measurement. This paper also discusses potential approaches to further reduce the inductance.
