Publications

Showing 36 results for Author: Narasinga Rao Miniskar

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  • Sep, 2026

    Journal

    Accl++ : A high-productivity programming language for performance and code portability on heterogeneous systems

    This work describes the Accl++ programming language for heterogeneous computing. Accl++ is embedded in the C++ language and implemented as a C++ library. The language allows for describing device code and execution libraries and includes primitives for runtime compilation (RTC), thereby enabling code portability across disparate devices. Here, we demonstrate Accl++’s capab…

  • Sep, 2026

    Conference Paper

    IRIS-MASH: Efficient Multi-device Asynchronous Multi-Stream Heterogeneous Computing

    In the rapidly evolving field of high-performance computing (HPC), effectively leveraging heterogeneous devices through asynchronous task programming is paramount. This paper presents a robust asynchronous task programming model tailored for a multi-device, multi-stream execution environment that incorporates a diverse array of heterogeneous computing units, including GPUs…

  • Jul, 2026

    Conference Paper

    PowerMappeR: Power-Optimized Mapping of SNNs onto ReRAM Crossbars coupled via Packet-Switched NoCs

    Many recent efforts in developing hardware-accelerated spiking neural networks (SNNs) are characterized by deep co-design between algorithms, architectures, and devices. Architectural advances overcome device constraints by coupling together many small resistive-RAM (ReRAM) crossbars via a network-on-chip (NoC) for neuromorphic component operation. Concurrently, improved S…

  • May, 2026

    Conference Paper

    Classic and Quantum Task-Based Intelligent Runtime for QIRs Running on Multiple QPUs

    High-performance computing systems are rapidly evolving into heterogeneous platforms that fuse quantum accelerators with traditional classical processing units (CPUs) and graphical processing units (GPUs). This convergence calls for runtimes capable of managing both classical and quantum workloads in a unified manner. We introduce an intelligent, task-based runtime that ma…

  • Mar, 2026

    Conference Paper

    IRIS: Exploring Performance Scaling of the Intelligent Runtime System and its Dynamic Scheduling Policies

    High-Performance Computing is becoming increasingly heterogeneous, relying on a diverse mix of hardware to achieve good performance. Paradoxically, current drivers and frameworks for these devices typically require separate languages and implementations for each vendor. Furthermore, there are few tools and little support to schedule codes between these devices in a truly h…

  • Mar, 2026

    Conference Paper

    IRIS-MEMFLOW: Data Flow-Enabled Portable Memory Orchestration in IRIS Runtime for Diverse Heterogeneity

    Task-based programming models and execution paradigms provide a means to decompose a computation by expressing it as a graph in which each node represents a specific computation operating on memory objects and the edges define the dependencies in the execution flow. In this execution model, independent nodes in the graph can be executed concurrently in different computing…

  • Mar, 2026

    Conference Paper

    An FPGA-Based Neuromorphic Processor with All-to-All Connectivity

    Neuromorphic computing is a promising paradigm for future energy-efficient computing. At present, however, it is in its nascent stages—most hardware implementations are research-grade, commercial products are not available, and the software tools are not production-ready. The lack of hardware and software tools makes neuromorphic computing inaccessible to researchers aroun…

  • Mar, 2026

    Conference Paper

    CHARM-SYCL & IRIS: A Tool Chain for Performance Portability on Extremely Heterogeneous Systems

    Performance portability is becoming crucial as high-performance computing systems become increasingly heterogeneous. We have many options for CPUs and accelerators (e.g., GPUs) but also for non-Von Neumann architectures such as field-programmable gate arrays. This paper presents the CHARM-SYCL unified programming environment for multiple accelerator types as a performance-…

  • Mar, 2026

    Conference Paper

    Neuro-Spark: A Submicrosecond Spiking Neural Networks Architecture for In-Sensor Filtering

    Neuro-Spark, which is a new neuromorphic architecture with a field-programmable gate array (FPGA) implementation for ultrafast spiking neural network (SNN) inference at the edge, facilitates smart-pixel in-sensor filtering for high-energy physics experiments at the Large Hadron Collider (LHC). Utilizing the evolutionary optimization for neuromorphic systems (EONS) training…

  • Mar, 2026

    Conference Paper

    IRIS Reimagined: Advancements in Intelligent Runtime System for Task-Based Programming

    Task-based programming models are gaining traction in scientific computing. IRIS is a portable runtime system that exploits multiple heterogeneous programming systems and can discover available resources and manage multiple diverse programming systems (e.g., CUDA, Hexagon, HIP, Level Zero, OpenCL, and OpenMP) simultaneously. It accounts for the constraints of task dependen…

  • Mar, 2026

    Conference Paper

    IRIS-GNN: Leveraging Graph Neural Networks for Scheduling on Truly Heterogeneous Runtime Systems

    The diversity of accelerators in computer systems poses significant challenges for software developers, such as managing vendor-specific compiler toolchains, code fragmentation requiring different kernel implementations, and performance portability issues. To address these, the Intelligent Runtime System (IRIS) was developed. IRIS works across various systems, from smartph…

  • Mar, 2026

    Conference Paper

    Characterizing GPU Energy Usage in Exascale-Ready Portable Science Applications

    We characterize the GPU energy usage of two widely adopted exascale-ready applications representing two classes of particle and mesh solvers: (i) QMCPACK, a quantum Monte Carlo package, and (ii) AMReX-Castro, an adaptive mesh astrophysical code. We analyze power, temperature, utilization, and energy traces from double-/single (mixed)-precision benchmarks on NVIDIA’s A100 a…

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