- By:
- Miniskar, Narasinga Rao ; Young, Aaron R; Asifuzzaman, Kazi ; Kulkarni, Shruti R; Date, Prasanna A; Bean, Alice; Vetter, Jeffrey S
- Page Number:
- 63-70
- Book Title:
- 2024 International Conference on Neuromorphic Systems (ICONS)
- Publication Date:
- March 12, 2026
- Publisher Location:
- IEEE, New Jersey, United States of America
- Conference Name:
- International Conference on Neuromorphic Systems (ICONS 2024)
- Conference Location:
- Arlington, Virginia, United States of America
- Conference Sponsor:
- IEEE
- View DOI Listing:
- https://doi.org/10.1109/ICONS62911.2024.00017
Abstract
Neuro-Spark, which is a new neuromorphic architecture with a field-programmable gate array (FPGA) implementation for ultrafast spiking neural network (SNN) inference at the edge, facilitates smart-pixel in-sensor filtering for high-energy physics experiments at the Large Hadron Collider (LHC). Utilizing the evolutionary optimization for neuromorphic systems (EONS) training method, we generate compact SNN models with 91% signal efficiency, akin to convolutional neural networks but with half the parameters. However, deploying near the detector poses a challenge because the SNN must handle a sustained input data rate exceeding 1013 GB/s. To overcome this, we propose a novel hardware architecture that uses high-level synthesis to construct a tuned architecture for the EONS-trained SNN. In addition to the analysis and validation with an AMD Xilinx Artix-A7 FPGA, our solution consumes only ç24% of FPGA LUT and flipflops. We also introduce an innovative quantization method that reduces FPGA resource utilization by ç15% without compromising accuracy. Our FPGA implementation achieves computing latency of ç10 ns for smart-pixel application inference on an edge FPGA.
