- By:
- Asifuzzaman, Kazi ; Miniskar, Narasinga Rao ; Godoy, William F; Hernandez Mendoza, Oscar R; Vetter, Jeffrey S
- Page Number:
- 42-47
- Book Title:
- GPGPU '25: Proceedings of the 17th Workshop on General Purpose Processing Using GPU
- Publication Date:
- March 12, 2026
- Publisher Location:
- Association for Computing Machinery, New York, United States of America
- Conference Name:
- The 17th Workshop on General Purpose Processing Using GPU (GPGPU)
- Conference Location:
- Las Vegas, Nevada, United States of America
- Conference Sponsor:
- N/A
- View DOI Listing:
- https://doi.org/10.1145/3725798.3725805
Abstract
In this work, we performed an initial design space exploration of an accelerated processing unit (APU)—a hybrid CPU+GPU architecture that integrates both compute units (CUs) and memory into a unified system. This integration aims to reduce data movement, enhance memory locality, and improve energy efficiency by enabling the CPU and GPU to share memory directly. This effort focused on the interplay of key design components—cache line size, the number of CUs, and main memory technology—and the trade-offs of each configuration were analyzed. This paper highlights the various configurations’ impact on memory accesses, data reuse, and power utilization. The results provide valuable insights that can be leveraged to optimize APU architectures for high-performance and energy-efficient computing and thus create a balanced architecture. This optimization can be achieved by adopting dynamic cache management, runtime CU scaling, and advanced memory integration, highlighting the potential of APUs to address critical challenges in compute, data movement, and memory power consumption.
